{"id":10,"date":"2023-04-09T07:39:10","date_gmt":"2023-04-09T07:39:10","guid":{"rendered":"http:\/\/localhost\/vnit\/physics\/?page_id=10"},"modified":"2026-11-03T07:04:41","modified_gmt":"2026-11-03T07:04:41","slug":"faculty","status":"publish","type":"page","link":"https:\/\/vnit.ac.in\/engineering\/cvlsi\/faculty\/","title":{"rendered":"Faculty"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-page\" data-elementor-id=\"10\" class=\"elementor elementor-10\">\n\t\t\t\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-38b21f9 elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"38b21f9\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-196dcaf\" data-id=\"196dcaf\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-cbd3ba9 elementor-widget elementor-widget-heading\" data-id=\"cbd3ba9\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.13.2 - 11-05-2023 *\/\n.elementor-heading-title{padding:0;margin:0;line-height:1}.elementor-widget-heading .elementor-heading-title[class*=elementor-size-]>a{color:inherit;font-size:inherit;line-height:inherit}.elementor-widget-heading .elementor-heading-title.elementor-size-small{font-size:15px}.elementor-widget-heading .elementor-heading-title.elementor-size-medium{font-size:19px}.elementor-widget-heading .elementor-heading-title.elementor-size-large{font-size:29px}.elementor-widget-heading .elementor-heading-title.elementor-size-xl{font-size:39px}.elementor-widget-heading .elementor-heading-title.elementor-size-xxl{font-size:59px}<\/style><h2 class=\"elementor-heading-title elementor-size-default\">Faculties at Centre for VLSI and Nanotechnology department<\/h2>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-c5a3fa6 elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"c5a3fa6\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-b49332a\" data-id=\"b49332a\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-791d6f7 elementor-position-top elementor-vertical-align-top elementor-widget elementor-widget-image-box\" data-id=\"791d6f7\" data-element_type=\"widget\" data-widget_type=\"image-box.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.13.2 - 11-05-2023 *\/\n.elementor-widget-image-box .elementor-image-box-content{width:100%}@media (min-width:768px){.elementor-widget-image-box.elementor-position-left .elementor-image-box-wrapper,.elementor-widget-image-box.elementor-position-right .elementor-image-box-wrapper{display:flex}.elementor-widget-image-box.elementor-position-right .elementor-image-box-wrapper{text-align:right;flex-direction:row-reverse}.elementor-widget-image-box.elementor-position-left .elementor-image-box-wrapper{text-align:left;flex-direction:row}.elementor-widget-image-box.elementor-position-top .elementor-image-box-img{margin:auto}.elementor-widget-image-box.elementor-vertical-align-top .elementor-image-box-wrapper{align-items:flex-start}.elementor-widget-image-box.elementor-vertical-align-middle .elementor-image-box-wrapper{align-items:center}.elementor-widget-image-box.elementor-vertical-align-bottom .elementor-image-box-wrapper{align-items:flex-end}}@media (max-width:767px){.elementor-widget-image-box .elementor-image-box-img{margin-left:auto!important;margin-right:auto!important;margin-bottom:15px}}.elementor-widget-image-box .elementor-image-box-img{display:inline-block}.elementor-widget-image-box .elementor-image-box-title a{color:inherit}.elementor-widget-image-box .elementor-image-box-wrapper{text-align:center}.elementor-widget-image-box .elementor-image-box-description{margin:0}<\/style><div class=\"elementor-image-box-wrapper\"><figure class=\"elementor-image-box-img\"><a href=\"https:\/\/vnit.ac.in\/engineering\/cvlsi\/dr-raghavendra-b-deshmukh\/\"><img loading=\"lazy\" decoding=\"async\" width=\"136\" height=\"153\" src=\"https:\/\/vnit.ac.in\/engineering\/cvlsi\/wp-content\/uploads\/2023\/10\/download.jpg\" class=\"attachment-full size-full wp-image-379\" alt=\"\" \/><\/a><\/figure><div class=\"elementor-image-box-content\"><h3 class=\"elementor-image-box-title\"><a href=\"https:\/\/vnit.ac.in\/engineering\/cvlsi\/dr-raghavendra-b-deshmukh\/\">\tDr. Raghavendra B. Deshmukh<\/a><\/h3><p class=\"elementor-image-box-description\"><b>Professor& Head of the Department <\/b><br>\nDigital Design, CMOS Design, Reconfigurable FPGA Design<\/p><\/div><\/div>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-f82969f elementor-widget elementor-widget-heading\" data-id=\"f82969f\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">PROFESSOR <\/h2>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<section class=\"elementor-section elementor-inner-section elementor-element elementor-element-1e499d4 elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"1e499d4\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-50 elementor-inner-column elementor-element elementor-element-adad58d\" data-id=\"adad58d\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-e68d705 elementor-position-top elementor-vertical-align-top elementor-widget elementor-widget-image-box\" data-id=\"e68d705\" data-element_type=\"widget\" data-widget_type=\"image-box.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<div class=\"elementor-image-box-wrapper\"><figure class=\"elementor-image-box-img\"><a href=\"https:\/\/vnit.ac.in\/engineering\/cvlsi\/dr-sanjay-b-dhok\/\"><img loading=\"lazy\" decoding=\"async\" width=\"768\" height=\"1024\" src=\"https:\/\/vnit.ac.in\/engineering\/cvlsi\/wp-content\/uploads\/2024\/05\/sbdphoto-768x1024.jpg\" class=\"attachment-large size-large wp-image-1223\" alt=\"\" srcset=\"https:\/\/vnit.ac.in\/engineering\/cvlsi\/wp-content\/uploads\/2024\/05\/sbdphoto-768x1024.jpg 768w, https:\/\/vnit.ac.in\/engineering\/cvlsi\/wp-content\/uploads\/2024\/05\/sbdphoto-225x300.jpg 225w, https:\/\/vnit.ac.in\/engineering\/cvlsi\/wp-content\/uploads\/2024\/05\/sbdphoto-1152x1536.jpg 1152w, https:\/\/vnit.ac.in\/engineering\/cvlsi\/wp-content\/uploads\/2024\/05\/sbdphoto-1536x2048.jpg 1536w, https:\/\/vnit.ac.in\/engineering\/cvlsi\/wp-content\/uploads\/2024\/05\/sbdphoto-scaled.jpg 1920w\" sizes=\"auto, (max-width: 768px) 100vw, 768px\" \/><\/a><\/figure><div class=\"elementor-image-box-content\"><h3 class=\"elementor-image-box-title\"><a href=\"https:\/\/vnit.ac.in\/engineering\/cvlsi\/dr-sanjay-b-dhok\/\">Dr. Sanjay B. Dhok<\/a><\/h3><p class=\"elementor-image-box-description\"><b>Professor <\/b><br>\nSignal Processing, Image Processing, Data Compression, Wireless Sensor Networks and VLSI Design<\/p><\/div><\/div>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t<div class=\"elementor-column elementor-col-50 elementor-inner-column elementor-element elementor-element-5b910d7\" data-id=\"5b910d7\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-98c1974 elementor-position-top elementor-vertical-align-top elementor-widget elementor-widget-image-box\" data-id=\"98c1974\" data-element_type=\"widget\" data-widget_type=\"image-box.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<div class=\"elementor-image-box-wrapper\"><figure class=\"elementor-image-box-img\"><a href=\"https:\/\/vnit.ac.in\/engineering\/cvlsi\/dr-ganesh-c-patil\/\"><img loading=\"lazy\" decoding=\"async\" width=\"150\" height=\"150\" src=\"https:\/\/vnit.ac.in\/engineering\/cvlsi\/wp-content\/uploads\/2026\/07\/download-2.jpg\" class=\"attachment-full size-full wp-image-1622\" alt=\"\" \/><\/a><\/figure><div class=\"elementor-image-box-content\"><h3 class=\"elementor-image-box-title\"><a href=\"https:\/\/vnit.ac.in\/engineering\/cvlsi\/dr-ganesh-c-patil\/\">Dr. Ganesh C. Patil<\/a><\/h3><p class=\"elementor-image-box-description\"><b> Professor <\/b><br>\n Device Physics and Modeling, Novel Nanoscale MOSFETs, Analog\/Digital CMOS circuits, VLSI System Design<\/p><\/div><\/div>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<div class=\"elementor-element elementor-element-b4541f6 elementor-widget elementor-widget-heading\" data-id=\"b4541f6\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">ASSOCIATE PROFESSOR <\/h2>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<section class=\"elementor-section elementor-inner-section elementor-element elementor-element-c7d5642 elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"c7d5642\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-33 elementor-inner-column elementor-element elementor-element-a5a7217\" data-id=\"a5a7217\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap\">\n\t\t\t\t\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t<div class=\"elementor-column elementor-col-33 elementor-inner-column elementor-element elementor-element-f7419da\" data-id=\"f7419da\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-324699b elementor-position-top elementor-vertical-align-top elementor-widget elementor-widget-image-box\" data-id=\"324699b\" data-element_type=\"widget\" data-widget_type=\"image-box.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<div class=\"elementor-image-box-wrapper\"><figure class=\"elementor-image-box-img\"><a href=\"https:\/\/vnit.ac.in\/engineering\/cvlsi\/dr-nikhil-deep-gupta\/\"><img loading=\"lazy\" decoding=\"async\" width=\"150\" height=\"150\" src=\"https:\/\/vnit.ac.in\/engineering\/cvlsi\/wp-content\/uploads\/2023\/10\/download4-150x150-1.jpg\" class=\"attachment-full size-full wp-image-376\" alt=\"\" \/><\/a><\/figure><div class=\"elementor-image-box-content\"><h3 class=\"elementor-image-box-title\"><a href=\"https:\/\/vnit.ac.in\/engineering\/cvlsi\/dr-nikhil-deep-gupta\/\">Dr. Nikhil Deep Gupta<\/a><\/h3><p class=\"elementor-image-box-description\"><b>Associate Professor<\/b><br>Photonics\/Optoelectronics Devices; Wide Band Gap Semiconductors; Power Electronics Devices; Electronics Process Integration   <\/p><\/div><\/div>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t<div class=\"elementor-column elementor-col-33 elementor-inner-column elementor-element elementor-element-7c6b1bc\" data-id=\"7c6b1bc\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap\">\n\t\t\t\t\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<div class=\"elementor-element elementor-element-a858e07 elementor-widget elementor-widget-heading\" data-id=\"a858e07\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">ASSISTANT  PROFESSOR<\/h2>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<section class=\"elementor-section elementor-inner-section elementor-element elementor-element-c8bd087 elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"c8bd087\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-33 elementor-inner-column elementor-element elementor-element-b8e9fce\" data-id=\"b8e9fce\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-b2c757f elementor-position-top elementor-vertical-align-top elementor-widget elementor-widget-image-box\" data-id=\"b2c757f\" data-element_type=\"widget\" data-widget_type=\"image-box.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<div class=\"elementor-image-box-wrapper\"><figure class=\"elementor-image-box-img\"><a href=\"https:\/\/vnit.ac.in\/engineering\/cvlsi\/dr-jailsingh-bhookya\/\" target=\"_blank\"><img loading=\"lazy\" decoding=\"async\" width=\"150\" height=\"150\" src=\"https:\/\/vnit.ac.in\/engineering\/cvlsi\/wp-content\/uploads\/2026\/10\/PRdc1-1.jpg\" class=\"attachment-full size-full wp-image-1739\" alt=\"\" \/><\/a><\/figure><div class=\"elementor-image-box-content\"><h3 class=\"elementor-image-box-title\"><a href=\"https:\/\/vnit.ac.in\/engineering\/cvlsi\/dr-jailsingh-bhookya\/\" target=\"_blank\">Dr. Jailsingh Bhookya<\/a><\/h3><p class=\"elementor-image-box-description\"><b>Assistant Professor<\/b><br>Electronic System Design, Embedded AI, Unmanned Aerial Vehicles (UAVs), Soft Robotics, Fractional-Order Modelling and Control, Flexible and Wearable Sensor-Array Fabrication<\/p><\/div><\/div>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t<div class=\"elementor-column elementor-col-33 elementor-inner-column elementor-element elementor-element-6715978\" data-id=\"6715978\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap\">\n\t\t\t\t\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t<div class=\"elementor-column elementor-col-33 elementor-inner-column elementor-element elementor-element-ac414ae\" data-id=\"ac414ae\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-0350bc7 elementor-position-top elementor-vertical-align-top elementor-widget elementor-widget-image-box\" data-id=\"0350bc7\" data-element_type=\"widget\" data-widget_type=\"image-box.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<div class=\"elementor-image-box-wrapper\"><figure class=\"elementor-image-box-img\"><a href=\"#\"><img loading=\"lazy\" decoding=\"async\" width=\"150\" height=\"150\" src=\"https:\/\/vnit.ac.in\/engineering\/cvlsi\/wp-content\/uploads\/2026\/10\/Photo-VNIT.jpg\" class=\"attachment-full size-full wp-image-1752\" alt=\"\" \/><\/a><\/figure><div class=\"elementor-image-box-content\"><h3 class=\"elementor-image-box-title\"><a href=\"#\">Dr. Girija Shankar Sahoo<\/a><\/h3><p class=\"elementor-image-box-description\"><b>Assistant Professor<\/b><br>Performance optimization and physical modelling of advanced solar cells (Perovskite, Kesterite CZTSSe, Multi-Junction, and Quantum-Structure photovoltaics) and nanoscale MOSFET\/TFET architectures<\/p><\/div><\/div>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<div class=\"elementor-element elementor-element-4a70d26 elementor-widget elementor-widget-heading\" data-id=\"4a70d26\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">Past Faculties<\/h2>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<section class=\"elementor-section elementor-inner-section elementor-element elementor-element-a1d4e5c elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"a1d4e5c\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-50 elementor-inner-column elementor-element elementor-element-932e7d0\" data-id=\"932e7d0\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-9981791 elementor-position-top elementor-vertical-align-top elementor-widget elementor-widget-image-box\" data-id=\"9981791\" data-element_type=\"widget\" data-widget_type=\"image-box.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<div class=\"elementor-image-box-wrapper\"><figure class=\"elementor-image-box-img\"><a href=\"https:\/\/vnit.ac.in\/engineering\/cvlsi\/dr-rajendra-m-patrikar\/\" target=\"_blank\"><img loading=\"lazy\" decoding=\"async\" width=\"137\" height=\"138\" src=\"https:\/\/vnit.ac.in\/engineering\/cvlsi\/wp-content\/uploads\/2023\/10\/Prof.-R.-M.-Patrikar.jpg\" class=\"attachment-thumbnail size-thumbnail wp-image-374\" alt=\"\" \/><\/a><\/figure><div class=\"elementor-image-box-content\"><h3 class=\"elementor-image-box-title\"><a href=\"https:\/\/vnit.ac.in\/engineering\/cvlsi\/dr-rajendra-m-patrikar\/\" target=\"_blank\">Dr. Rajendra M. Patrikar<\/a><\/h3><p class=\"elementor-image-box-description\"><b>Professor (Retired)<\/b><\/p><\/div><\/div>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t<div class=\"elementor-column elementor-col-50 elementor-inner-column elementor-element elementor-element-a57bc79\" data-id=\"a57bc79\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-6f72f64 elementor-position-top elementor-vertical-align-top elementor-widget elementor-widget-image-box\" data-id=\"6f72f64\" data-element_type=\"widget\" data-widget_type=\"image-box.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<div class=\"elementor-image-box-wrapper\"><figure class=\"elementor-image-box-img\"><a href=\"https:\/\/vnit.ac.in\/engineering\/cvlsi\/dr-vasu-pulijala\/\"><img loading=\"lazy\" decoding=\"async\" width=\"150\" height=\"150\" src=\"https:\/\/vnit.ac.in\/engineering\/cvlsi\/wp-content\/uploads\/2026\/07\/download-3.jpg\" class=\"attachment-thumbnail size-thumbnail wp-image-1617\" alt=\"\" \/><\/a><\/figure><div class=\"elementor-image-box-content\"><h3 class=\"elementor-image-box-title\"><a href=\"https:\/\/vnit.ac.in\/engineering\/cvlsi\/dr-vasu-pulijala\/\">Dr. Vasu Pulijala<\/a><\/h3><p class=\"elementor-image-box-description\"><b>Assistant Professor <\/b><\/p><\/div><\/div>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>Faculties at Centre for VLSI and Nanotechnology department Dr. Raghavendra B. Deshmukh Professor&#038; Head of the Department Digital Design, CMOS Design, Reconfigurable FPGA Design PROFESSOR Dr. Sanjay B. Dhok Professor Signal Processing, Image Processing, Data Compression, Wireless Sensor Networks and VLSI Design Dr. Ganesh C. Patil Professor Device Physics and Modeling, Novel Nanoscale MOSFETs, Analog\/Digital [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-10","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/vnit.ac.in\/engineering\/cvlsi\/wp-json\/wp\/v2\/pages\/10","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/vnit.ac.in\/engineering\/cvlsi\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/vnit.ac.in\/engineering\/cvlsi\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/vnit.ac.in\/engineering\/cvlsi\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/vnit.ac.in\/engineering\/cvlsi\/wp-json\/wp\/v2\/comments?post=10"}],"version-history":[{"count":85,"href":"https:\/\/vnit.ac.in\/engineering\/cvlsi\/wp-json\/wp\/v2\/pages\/10\/revisions"}],"predecessor-version":[{"id":1780,"href":"https:\/\/vnit.ac.in\/engineering\/cvlsi\/wp-json\/wp\/v2\/pages\/10\/revisions\/1780"}],"wp:attachment":[{"href":"https:\/\/vnit.ac.in\/engineering\/cvlsi\/wp-json\/wp\/v2\/media?parent=10"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}